Exemplary embodiments of the present invention relate to a semiconductor device and a method for fabricating the same, and more particularly, to a three dimensional 3D nonvolatile memory device and a method for fabricating the same.
Nonvolatile memory devices maintain data stored therein, even though power supply is cut off. Recently, as the increase in integration degree of two dimensional (2D) memory devices in which memory cells are formed as a single layer on a silicon substrate approaches the limit, 3D nonvolatile memory devices in which memory cells are vertically stacked from a silicon substrate have been proposed.
Hereafter, a conventional method for fabricating a 3D nonvolatile memory device will be described with FIGS. 1A to 1D.
FIGS. 1A to 1C are cross-sectional views illustrating a conventional method for fabricating a 3D nonvolatile memory device. In particular, FIGS. 1A to 1C are process diagrams explaining a method for fabricating a vertical channel nonvolatile memory device in which strings are vertically arranged on a substrate.
Referring to FIG. 1A, a plurality of interlayer dielectric layers 11 and gate electrode conductive layers 12 are alternately formed over a substrate 10, and then etched to form a plurality of trenches exposing the substrate 10.
A gate dielectric layer 13 is formed on the inner walls of the trenches, and a channel formation layer is buried in the trenches having the gate dielectric layer 13 formed on the inner walls thereof, thereby forming a plurality of channels CH. Accordingly, a lower select transistor LST is formed.
Referring to FIG. 1B, a plurality of interlayer dielectric layers 14 and gate electrode conductive layers 15 are alternately formed over the resultant structure having the lower select transistor LST formed on the inner walls thereof, and then are etched to form a plurality of trenches exposing the respective channels CH of the lower select transistor LST.
A charge blocking layer, a charge trap layer, and a tunnel insulating layer are sequentially formed on the inner walls of the trenches. For convenience of description, the charge blocking layer, the charge trap layer, and the tunnel insulating layer are illustrated as one layer represented by reference numeral 16.
A channel formation layer is buried in the trenches having the charge blocking layer, the charge trap layer, and the tunnel insulating layer formed on the inner walls thereof, thereby forming a plurality of channels CH. Accordingly, a plurality of memory cells MC are formed.
Referring to FIG. 1C, a plurality of interlayer dielectric layers 17 and gate electrode conductive layers 18 are alternately formed over the resultant structure having the plurality of memory cells MC formed therein, and are subsequently etched to form a plurality of trenches exposing the channels CH of the memory cells MC.
A gate dielectric layer 19 is formed on the inner walls of the trenches, and a channel formation layer is buried in the trenches having the gate dielectric layer 19 formed on the inner walls thereof, thereby forming a plurality of channels CH. Accordingly, an upper select transistor UST is formed.
In accordance with the above-described conventional method for forming a 3D nonvolatile memory device, the lower select transistor LST, the plurality of memory cells MC, and the upper select transistor UST, which are stacked over the substrate 10, constitute one string ST. When the strings ST are vertically arranged from the substrate 10, the integration degree of the memory device may be increased, compared with a conventional 2D nonvolatile memory device.
In the conventional method for forming a 3D nonvolatile memory device, however, the fabricating process is complex, and the arrangement of the channels CH is not relatively easy to perform. Furthermore, since the widths of the channels CH are not uniform, a concern is raised in controlling a threshold voltage. Such a concern will be described below in more detail.
First, in accordance with the conventional method for fabricating a 3D nonvolatile memory device, the plurality of memory cells MC and the upper select transistor UST are sequentially formed after the lower select transistor LST is formed on the substrate 10. That is, since one string is formed through at least three steps, the fabricating process becomes relatively complex, and the fabricating cost may increase.
Furthermore, the respective channels CH of the lower select transistor LST, the memory cells MC, and the upper select transistor UST are desired to be aligned for being integrally connected. However, the channels CH may not easily align with each other, due to the process limitation. In particular, since the overlay control margin decreases as the integration degree of the memory device increases, the channels CH may be further misaligned with each other as the integration degree of the memory device increases.
Second, when the strings are vertically arranged on the substrate 10, the plurality of interlayer dielectric layers 14 and the plurality of gate electrode conductive layers 15 are etched by one process to form the trench for the plurality of memory cells MC. That is, the trench having a high aspect ratio is formed. However, the width of the trench may decrease toward the lower part of the trench, due to the limitation of the etching process. Such a concern is illustrated in FIG. 1D.
FIG. 1D is a diagram showing an expanded view of a cross-section of the above-described intermediate structure of FIG. 1B in the area denoted by A in FIG. 1B. Referring to FIG. 1D, it can be seen that the width of the channel CH decreases toward the lower part thereof. That is, the memory cells MC formed in the upper part of the intermediate structure have a larger channel width W2 than the memory cells MC formed in the lower part thereof, which have a channel width W1. Such a difference in the channel widths among the plurality of memory cells MC makes the threshold voltage of the memory cells MC non-uniform. Thus, there is a concern in controlling the threshold voltage of the memory cells.
In particular, since the number of memory cells MC to be stacked increases with the increase in integration degree of memory devices, the depth of the trench is further increased with the increase in integration degree of memory devices. Accordingly, such a concern with controlling the threshold voltage of memory cells becomes more significant.